The present invention relates to a semiconductor memory device, and particularly to art that can be effectively adapted to writing/reading data with many bits as a unit such as an address tag or data in a cache memory.
When many bits are to be simultaneously read out such as in a cache memory, it becomes necessary to provide a parity check function and an address comparison function These functions must be carried out at high speeds and realized in a highly dense integrated form. It is further desired to shorten the rise time of the word line to the time needed for amplification of data stored in a selected memory cell by the sense amplifier; i.e, it is desired to increase the speed of reading operation. Also, by using a static memory cell, in general, it becomes possible to increase the speed of reading operation. Further, operation of the sense amplifiers has been disclosed in Japanese Patent Laid-Open Nos. 53-73039, 52-21733, 57-198592 and in Electronic Technology, Vol. 23, No. 3, 1981, pp 31-32. Japanese Patent Laid-Open No. 53-73039 discloses an art in which the signal input gates (QN4 and QN5) for the sense amplifier are automatically rendered nonconductive simultaneously with the start of amplification by the sense amplifier. But it does not disclose any concrete constitution for reading many bits simultaneously. This prior art does not disclose any concrete operation for writing the data, either. Further, the above: Japanese Patent Laid-Open No. 52-21733, Japanese Patent Laid-Open No. 57-198592 and Electronic Technology Vol. 23, No. 3 all disclose memories having a relationship between a sense amplifier and switch means for inputting signals to the sense amplifier. The above memories, however, are all of the dynamic type.